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TSL202R 128 1 linear sensor array taos032f ? january 2012 1 the lumenology company copyright 2012, taos inc. www.taosinc.com 128 1 sensor-element organization 200 dots-per-inch (dpi) sensor pitch high linearity and uniformity wide dynamic range . . . 2000:1 (66 db) output referenced to ground low image lag . . . 0.5% typ operation to 5 mhz single 5-v supply replacement for tsl202 description the TSL202R linear sensor array consists of two sections of 64 photodiodes and associated charge amplifier circuitry ar ranged to form a contiguous 128 1 array. the pixels measure 120 m (h) by 70 m (w) with 125-m center-to-center spacing and 55-m spacing between pixels. operation is simplified by internal control logic that requires only a serial-input (si) signal and a clock. the TSL202R is intended for use in a wide variety of applications including mark detection and code reading, optical character recognition (ocr) and contact imaging, edge detection and positioning as well as optical linear and rotary encoding. functional block diagram (each section ? pin numbers apply to section 1) 2 3 si clk 64-bit shift register q64 switch control logic pixel 2 pixel 64 pixel 3 analog bus q3 q2 q1 output amplifier gain trim v dd ao gnd 5 1 4 r l (external 330 load) integrator reset _ + pixel 1 sample/ output s1 s2 2 1 3 1 2 texas advanced optoelectronic solutions inc. 1001 klein road suite 300 plano, tx 75074 (972) 673-0759 (top view) nc ? no internal connection ? ? ? ? ? v dd 1 si1 2 clk 3 ao1 4 gnd 5 so2 6 nc 7 14 nc 13 so1 12 gnd 11 nc 10 si2 9 nc 8 ao2 ams ag technical content still valid
TSL202R 128 1 linear sensor array taos032f ? january 2012 2 copyright 2012, taos inc. the lumenology company www.taosinc.com terminal functions terminal name no. description ao1 4 analog output of section 1 ao2 8 analog output of section 2 clk 3 clock. clk controls charge transfer, pixel output, and reset. gnd 5,12 ground (substrate). all voltages are referenced to gnd. nc 7, 9, 11, 14 no internal connection si1 2 serial input (section 1). si1 defines the start of the data-out sequence. si2 10 serial input (section 2). si2 defines the start of the data-out sequence. so1 13 serial output (section 1). so1 provides a signal to drive the si2 input. so2 6 serial output (section 2). so2 provides a signal to drive the si input of another device for cascading or as an end-of-data indication. v dd 1 supply voltage. supply voltage for both analog and digital circuitry. detailed description the sensor consists of 128 photodiodes arranged in a linear array. light energy impinging on a photodiode generates photocurrent, which is integrated by the active integration circuitry associated with that pixel. during the integration period, a sampling capacitor connects to the output of the integrator through an analog switch. the amount of charge accumulated at each pixel is directly proportional to the light intensity and the integration time. the integration time is the interval between two consecutive output periods. the output and reset of the integrators is controlled by a 128-bit shift register and reset logic. an output cycle is initiated by clocking in a logic 1 on si for one positive going clock edge (see figures1 and 2) ? . as the si pulse is clocked through the 128-bit shift register, the charge on the sampling capacitor of each pixel is sequentially connected to a charge-coupled output amplifier that generates a voltage outpu t, ao. when the bit position goes low, the pixel integrator is reset. on the 129 th clock rising edge, the si pulse is clocked out of the shift register and the output assumes a high-impedance state. note that this 129 th clock pulse is required to terminate the output of the 128 th pixel and return the internal logic to a known state. a subsequent si pulse can be presented as early as the 130 th clock pulse, thereby initiating another pixel output cycle. the voltage developed at analog output (ao) is given by: v out = v drk + (r e ) (e e ) (t int ) where: v out is the analog output voltage for white condition v drk is the analog output voltage for dark condition r e is the device responsivity for a given wavelength of light given in v/( j/cm 2 ) e e is the incident irradiance in w/cm 2 t int is integration time in seconds ao is driven by a source follower that requires an external pulldown resistor (330- typical). the output is nominally 0 v for no light input, 2 v for normal white-level, and 3.4 v for saturation light level. when the device is not in the output phase, ao is in a high impedance state. a 0.1 f bypass capacitor should be connected between v dd and ground as close as possible to the device. ? for proper operation, after meeting the minimum hold time condition, si must go low before the next rising edge of the clock. ams ag technical content still valid
TSL202R 128 1 linear sensor array taos032f ? january 2012 3 the lumenology company copyright 2012, taos inc. www.taosinc.com absolute maximum ratings ? supply voltage range, v dd ?0.3 v to 6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v i ?0.3 v to v dd + 0.3v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input clamp current, i ik (v i < 0 or v i > v dd ) ?20 ma to 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output clamp current, i ok (v o < 0 or v o > v dd ) ?25 ma to 25 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . voltage range applied to any output in the high impedance or power-off state, v o ?0.3 v to v dd + 0.3v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous output current, i o (v o = 0 to v dd ) ?25 ma to 25 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous current through v dd or gnd ?40 ma to 40 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . analog output current range, i o ?25 ma to 25 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating free-air temperature range, t a ?25 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg ?25 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . esd tolerance, human body model 2000 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, a nd functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating conditions? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions (see figure 1 and figure 2) min nom max unit supply voltage, v dd 4.5 5 5.5 v input voltage, v i 0 v dd v high-level input voltage, v ih 2 v dd v low-level input voltage, v il 0 0.8 v wavelength of light source, 400 1000 nm clock frequency, f clock 5 5000 khz sensor integration time, serial, t int 0.026 100 ms sensor integration time, parallel, t int 0.013 100 ms operating free-air temperature, t a 0 70 c load resistance, r l 300 4700 load capacitance, c l 420 pf ams ag technical content still valid
TSL202R 128 1 linear sensor array taos032f ? january 2012 4 copyright 2012, taos inc. the lumenology company www.taosinc.com electrical characteristics at f clock = 1 mhz, v dd = 5 v, t a = 25 c, p = 640 nm, t int = 5 ms, r l = 330 , e e = 16.5 w/cm 2 (unless otherwise noted) parameter test conditions min typ max unit v out analog output voltage (white, average over 128 pixels) see note 1 1.6 2 2.4 v v drk analog output voltage (dark, average over 128 pixels) 0 50 150 mv prnu pixel response nonuniformity see notes 2 & 3 4% 10% nonlinearity of analog output voltage see note 3 0.4% fs output noise voltage see note 4 1 mvrms r e responsivity 18 23 30 v/ ( j/cm 2 ) se saturation exposure see note 5 142 nj/cm 2 v sat analog output saturation voltage 2.5 3.4 v dsnu dark signal nonuniformity all pixels see note 6 25 120 mv il image lag see note 7 0.5% i dd supply current, output idle 7 10 ma i ih high-level input current v i = v dd 10 a i il low-level input current v i = 0 10 a v o high level output voltage so1 and so2 i o = 50 a 4.5 4.95 v v oh high-level output voltage, so1 and so2 i o = 4 ma 4.6 v v o low level output voltage so1 and so2 i o = 50 a 0.01 0.1 v v ol low-level output voltage, so1 and so2 i o = 4 ma 0.4 v c i(si) input capacitance, si 5 pf c i(clk) input capacitance, clk 10 pf notes: 1. the array is uniformly illuminated with a diffused led source having a peak wavelength of 640 nm. 2. prnu is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of th e device under test when the array is uniformly illuminated at the white irradiance level. prnu includes dsnu. 3. nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent of analog output voltage (white). 4. rms noise is the standard deviation of a single-pixel output under constant illumination as observed over a 5-second period. 5. minimum saturation exposure is calculated using the minimum v sat , the maximum v drk , and the maximum r e . 6. dsnu is the difference between the maximum and minimum output voltage in the absence of illumination. 7. image lag is a residual signal left in a pixel from a previous exposure. it is defined as a percent of white-level signal remaining after a pixel is exposed to a white condition followed by a dark condition: il v out (il) v drk v out (white) v drk 100 timing requirements (see figure 1 and figure 2) min nom max unit t su(si) setup time, serial input (see note 8) 20 ns t h(si) hold time, serial input (see note 8 and note 9) 0 ns t w pulse duration, clock high or low 50 ns t r , t f input transition (rise and fall) time 0 500 ns notes: 8. input pulses have the following characteristics: t r = 6 ns, t f = 6 ns. 9. si must go low before the rising edge of the next clock pulse. ams ag technical content still valid
TSL202R 128 1 linear sensor array taos032f ? january 2012 5 the lumenology company copyright 2012, taos inc. www.taosinc.com dynamic characteristics over recommended ranges of supply voltage and operating free-air temperature (see figure 2) parameter test conditions min typ max unit t s analog output settling time to 1% r l = 330 , c l = 10 pf 185 ns t pd(so) propagation delay time, so1, so2 50 ns typical characteristics ???????????????????? ???????????????????? ???????? ???????? 129 clock cycles clk si ao hi-z hi-z figure 1. timing waveforms ao1 (a02) si1 (si2) clk pixel 64 (128) t s 0 v 0 v 5 v 2.5 v t h(si) 5 v t su(si) t w 1 (65) 2 (66) 64 (128) 65 (129) t s pixel 1 (65) 2.5 v 2.5 v 2.5 v 2.5 v t pd(so) t pd(so) so1 (so2) figure 2. operational waveforms (each section) ams ag technical content still valid
TSL202R 128 1 linear sensor array taos032f ? january 2012 6 copyright 2012, taos inc. the lumenology company www.taosinc.com typical characteristics 0.4 0 300 500 700 900 0.6 0.8 photodiode spectral responsivity 0.2 ? wavelength ? nm normalized responsivity t a = 25 c 1 1100 400 600 800 1000 figure 3 figure 4 analog output settling time vs load capacitance and resistance r l ? load resistance ? 200 0 0 400 800 1200 300 400 100 v dd = 5 v v out = 1 v 500 200 600 1000 t s ? settling time to 1% ? ns 600 100 pf 470 pf 220 pf 10 pf ams ag technical content still valid
TSL202R 128 1 linear sensor array taos032f ? january 2012 7 the lumenology company copyright 2012, taos inc. www.taosinc.com application information power supply considerations for optimum device performance, power-supply lines should be decoupled by a 0.01- f to 0.1-f capacitor with short leads mounted close to the device package (see figure 5 and figure 6). integration time the integration time of the linear array is the period during which light is sampled and charge accumulates on each pixel?s integrating capacitor. the flexibility to adjust the integration period is a powerful and useful feature of the taos tsl2xx linear array family. by changing the integration time, a desired output voltage can be obtained on the output pin while avoiding saturation for a wide range of light levels. each pixel of the linear array consists of a light-sensitive photodiode. the photodiode converts light intensity to a voltage. the voltage is sampled on the sampling capacitor by closing switch s2 (position 1) (see the functional block diagram on page 1). logic controls the resetting of the integrating capacitor to zero by closing switch s1 (position 2). at si input (start integration), pixel 1 is accessed. during this event, s2 moves from position 1 (sampling) to position 3 (holding). this holds the sampled voltage for pixel 1. switch s1 for pixel 1 is then moved to position 2. this resets (clears) the voltage previously integrated for that pixel so that pixel 1 is now ready to start a new integration cycle. when the next clock period starts, the s1 switch is returned to position 1 to be ready to start integrating again. s2 is returned to position 1 to start sampling the next light integration. then the next pixel starts the same procedure. the integration time is the time from a specific pixel read to the next time that pixel is read again. if either the clock speed or the time between successive si pulses is changed, the integration time will vary. after the final (n th ) pixel in the array is read on the output, the output goes into a high-impedance mode. a new si pulse can occur on the ( n +1) clock causing a new cycle of integration/output to begin. note that the time between successive si pulses must not exceed the maximum integration time of 100 msec. the minimum integration time for any given array is determined by time required to clock out all the pixels in the array and the time to discharge the pixels. the time required to discharge the pixels is a constant. therefore, the minimum integration period is simply a function of the clock frequency and the number of pixels in the array. a slower clock speed increases the minimum integration time and reduces the maximum light level for saturation on the output. the minimum integration time shown in this data sheet is based on the maximum clock frequency of 5 mhz. the minimum integration time can be calculated from the equation: t int(min) 1 maximum clock frequency n where: n is the number of pixels in the case of the TSL202R, the minimum integration time would be: t int(min) 200 ns 128 25.6 s it is important to note that not all pixels will have the same integration time if the clock frequency is varied while data is being output. ams ag technical content still valid
TSL202R 128 1 linear sensor array taos032f ? january 2012 8 copyright 2012, taos inc. the lumenology company www.taosinc.com application information it is good practice on initial power up to run the clock ( n +1) times after the first si pulse to clock out indeterminate data from power up. after that, the si pulse is valid from the time following ( n +1) clocks. the output will go into a high-impedance state after the n +1 high clock edge. it is good practice to leave the clock in a low state when inactive because the si pulse required to start a new cycle is a low-to-high transition. the integration time chosen is valid as long as it falls in the range between the minimum and maximum limits for integration time. if the amount of light incident on the array during a given integration period produces a saturated output (max voltage output), then the data is not accurate. if this occurs, the integration period should be reduced until the analog output voltage for each pixel falls below the saturation level. the goal of reducing the period of time the light sampling window is active is to lower the output voltage level to prevent saturation. however, the integration time must still be greater than or equal to the minimum integration period. if the light intensity produces an output below desired signal levels, the output voltage level can be increased by increasing the integration period provided that the maximum integration time is not exceeded. the maximum integration time is lim ited by the length of time the integrating capacitors on the pixels can hold their accumulated charge. the maximum integration time should not exceed 100 ms for accurate measurements. although the linear array is capable of running over a wide range of operating frequencies up to a maximum of 5 mhz, the speed of the a/d converter used in the application is likely to be the limiter for the maximum clock frequency. the voltage output is available for the whole period of the clock, so the setup and hold times required for the analog-to-digital conversion must be less than the clock period. ams ag technical content still valid
TSL202R 128 1 linear sensor array taos032f ? january 2012 9 the lumenology company copyright 2012, taos inc. www.taosinc.com application information connection diagrams 1 2 3 4 5 6 7 14 13 12 11 10 9 8 v dd si1 clk ao1 gnd so2 v dd nc so1 gnd nc si2 nc ao2 si clk ao v dd 0.1 f TSL202R r l figure 5. serial connection 1 2 3 4 5 6 7 14 13 12 11 10 9 8 v dd si1 clk ao1 gnd so2 v dd nc so1 gnd nc si2 nc ao2 si clk ao2 (pixels 65 ?128) ao1 (pixels 1? 64) r l v dd 0.1 f TSL202R r l figure 6. parallel connection ams ag technical content still valid
TSL202R 128 1 linear sensor array taos032f ? january 2012 10 copyright 2012, taos inc. the lumenology company www.taosinc.com mechanical information this assembly consists of 2 sensor chips mounted on a printed-circuit board in a clear molded plastic package. top of die to top of package ?????? ??????????? 1234567 14 13 12 11 10 9 8 ?????? top view side view bottom view 14 4.60 min 14 0.508 0.406 end view 1.90 0.76 7.87 7.37 2 2.16 1.42 0.89 1.29 14 0.50 0.00 3.18 2.79 0.53 0.28 pin 1 indicator 19.30 18.29 12 2.54 nonaccumulative see note b 10.67 9.65 sensors c l 3.62 3.92 sensors to pin 1 pixel 1 to pin 1 notes: a. all linear dimensions are in millimeters. b. the true-position spacing is 2.54 mm between lead centerlines. each pin centerline is located within 0.25 mm of its true longitudinal positions. c. index of refraction of clear plastic is 1.52. d. this drawing is subject to change without notice. figure 7. packaging configuration ams ag technical content still valid
TSL202R 128 1 linear sensor array taos032f ? january 2012 11 the lumenology company copyright 2012, taos inc. www.taosinc.com soldering information tsl202 128 1 linear array 14-lead gold pin package soldering instructions: the TSL202R has been designed to withstand a lead temperature during soldering of 260 c for 10 seconds at a distance of 1.6 mm from the package body. in most applications, these through-hole parts will be sufficiently protected by the combination of the pcb or flex plus the standoff provided by the package. if lead clipping is required, this should be performed after solder attach to prevent the pulling of the lead from the package body. as in all board manufacturing, care should be taken to prevent part bending during board singulation or final assembly. if the process includes both surface-mount parts and the TSL202R, the surface mount operations should be completed first with the through-hole parts afterward. these parts can be washed as a part of the flux cleanup operation. a final top-surface cleanup may be required with water or alcohol to remove any remaining particles. ams ag technical content still valid
TSL202R 128 1 linear sensor array taos032f ? january 2012 12 copyright 2012, taos inc. the lumenology company www.taosinc.com production data ? information in this document is current at publication date. products conform to specifications in accordance with the terms of texas advanced optoelectronic solutions, inc. standard warranty. production processing does not necessarily include testing of all parameters. notice texas advanced optoelectronic solutions, inc. (t aos) reserves the right to make changes to the products contained in this document to improve performance or for any other purpose, or to discontinue them without notice. customers are advised to contact taos to obtain the latest product information before placing orders or designing taos products into systems. taos assumes no responsibility for the use of any products or circuits described in this document or customer product design, conveys no license, either expressed or implied, under any patent or other right, and makes no representation that the circuits are free of patent infringement. taos further makes no claim as to the suitability of its products for any particu lar purpose, nor does taos assume any liability arising out of the use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. texas advanced optoelectronic solutions, inc. products are not designed or intended for use in critical applications in which the failure or malfunction of the taos product may result in personal injury or death. use of t aos products in life support systems is expressly unauthorized and any such use by a customer is completely at the customer?s risk. lumenology, taos, the taos logo, and texas advanced optoelectronic solutions are registered trademarks of texas advanced optoelectronic solutions incorporated. ams ag technical content still valid

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